In a computer, one or more caches with a small capacity and a high access speed are usually designed between a processor and a memory, for temporarily storing partial data in the memory to facilitate fast access of the processor to data in the cache.
Recently, with the development of computer technologies, multiprocessor systems are widely applied. In a multiprocessor system such as a cache-coherent non uniform memory-access architecture (Cache-Coherent Non Uniform Memory-access Architectures, CC-NUMA), multiple processors are connected together through a node controller (Node Controller, NC) to share the memory. Specifically, when specific data is required, a certain processor X first accesses a local cache, and if the local cache is not hit, that is, the local cache does not have the specific data required by the processor, a request for sending the specific data is sent to a remote address through a local NC. Because the multiple processors share the memory, and the remote cache may store the data required by the processor X, if read access hits a remote cache, and the remote cache stores the specific data required by the processor X, the data is sent to the processor X that initially sends a data request. Therefore, if the data required by the processor is in a remote cache with a long transmission path in a network topology, a time delay occurring when accessing the remote cache is long, and the cache access efficiency is reduced.
In order to improve the local data hit rate and the cache access efficiency, in the prior art, a remote dedicated cache is added on the node controller, for temporarily storing data at a remote address. Specifically, in the case that the access to the local cache is not hit, the processor accesses the remote dedicated cache, and if the remote dedicated cache is still not hit, the processor accesses the remote cache corresponding to the remote address. By storing data of a remote memory in a local remote dedicated cache, the time of access to the remote memory data of the processor is shortened and the local data hit rate and the cache access efficiency are improved.
In the process of accessing the cache, the inventor finds that the prior art at least has the following problem: as the remote dedicated cache is underlying hardware added for a local physical layer, and cannot be identified by a node controller on a protocol layer, an interface module of the remote dedicated cache needs to be separately designed, so that the problem of high development costs occurs.